M. Tech (VLSI Design), IIIT, Gwalior (India)
B. Tech (ECE), U.P.T.U, Lucknow (India)
Low power VLSI design, low power and high speed FPGA design, CMOS digital IC design
Pankaj Kumar joined G D Goenka World Institute-Lancaster University in August 2013 as an Assistant Professor in electronic and electrical engineering. Prior to this he was Assistant Professor at Manav Rachna International University, Faridabad. He also worked as a lecturer at Sachdeva Institute of Technology, Mathura (Affiliated to U.P.T.U, Lucknow).
Pankaj completed a M. Tech in VLSI Design from Indian Institute of Information Technology and Management, Gwalior and a B. Tech. in electronics and communications engineering from Uttar Pradesh Technical University, Lucknow.
Pankaj has published several research papers in journals and conferences of international and national repute. He has supervised dissertations and projects at M. Tech and B. Tech levels in the area of VLSI design and embedded systems.
Research and Publications
- ‘Design and Analysis of GDI Based Full Adder Circuit for Low Power Applications’, International Journal of Engineering Research and Applications, 4(3), pp. 462-465. (Kumar, P., and Yadav, P., 2014)
- ‘Performance Analysis of GDI based 1-bit Full Adder Circuit for Low Power and High Speed Applications’, International Journal of VLSI and Embedded Systems, 4(3), pp. 386-389. (Yadav, P., and Kumar, P., 2013)
- ‘Noise Tolerance Enhancement with Leakage Current Reduction in Dynamic Logic Circuits’, International Journal of Scientific Engineering and Technology, 1(3), pp. 137-142. (Dutta, U., Kumar, P., Kumar, N., 2012).
- ‘Performance Analysis of 90 nm Look Up Table (LUT) for Low Power Application’ Thirteenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Lille, France, pp. 404–407. (Kumar, P., Kumar, D., Pattanaik, M., September 2010).
- ‘Performance Analysis of Dynamic Threshold MOS (DTMOS) based 4-input Multiplexer Switch for Low Power and High Speed FPGA design’, IEEE/ACM Twenty Third Symposium on Integrated Circuits and Systems Design, Sao Paula, Brazil, pp. 2–7. (Kumar, D., Kumar, P., Pattanaik, M., September 2010).
- ‘Future Challenges in Nano CMOS Technology: A brief Review’, ‘International Conference on Advances in Nanotechnology, Raipur, India. (Kumar, P., Singh, P., Pattanaik, M., Srivastava, A., November 2008)
- ‘Low Leakage and High Speed Dynamic Threshold SRAM (DTSRAM) Design for Deep submicron FPGA Applications’ Second National Conference on Communication Networks, Kerala, India. (Kumar, P., Yadav, A., Pattanaik, M., April 2010)
- ‘A New Gate Diffusion Input (GDI) based 1-bit Magnitude comparator For Low Power and High Speed Operation’, National Conference on Emerging Electronic and Computing Systems, Indore, India. (Kumar, P., Yadav, A., Pattanaik, M., April 2010)
Prior to joining the GD Goenka World Institute, he was Assistant Prof. with Manav Rachna International University, Faridabad, Lecturer in Sachdeva Institute of Technology, Mathura ( Affiliated to U.P.T.U , Lucknow)
Achievement and Awards
- Scholarship from the Ministry of HRD, Govt. of India for pursuing M. Tech
- Certificate in “Telecom Terminal Technologies” training program conducted by C-DAC Mohali (Chandigarh).